From silica to tokens
AI is not one supply chain. It is a set of nested production systems: materials become tools, tools make wafers, dies meet memory inside packages, packages mount onto boards, boards fill racks, and racks wait for power. Follow the constraint, then ask who owns the qualified capacity.
01 / End-to-end map
Select a node to see its job, common bottlenecks, the KPI trail, and representative companies. Arrows mean physical or economic dependency, not that every company buys directly from the next.
02 / Market heatmap crosswalk
The Morgan Stanley exhibit organizes investable beneficiaries by owner and product bucket. The atlas organizes physical and economic dependency. This overlay reconciles every named box without pretending capital owners, manufacturing processes, and components are the same kind of node.
Coverage here means the component or ownership category is explicitly placed. It does not mean every logo in the exhibit is included, investable, correctly valued, or a pure-play beneficiary.
03 / The confusing middle
This is where “substrate,” “laminate,” “board,” and “package” get mixed together. The same upstream chemistry and process logic can feed different products with very different tolerances.
Fine electronic-grade glass filaments spun from specialty glass compositions.
A woven reinforcement. Low-CTE and low-loss grades help control warpage and signal integrity.
Copper-clad laminate: glass cloth impregnated with resin and bonded to copper foil.
CCL is patterned, drilled, plated, stacked, and laminated into a printed circuit board.
The PCB carries GPUs, CPUs, networking, power stages, connectors, and thousands of passives.
The market usually means electronic-grade glass fiber cloth, sometimes specifically low-CTE glass cloth such as T-glass. It is not a cleanroom wipe and it is not copper foil. It reinforces CCL, which is then processed into PCB. When AI boards become larger, faster, hotter, and more multilayered, flatter and lower-loss cloth can become a qualification bottleneck.
Think of high-speed CCL as a sandwich recipe. The resin controls much of the electrical loss, the cloth keeps the sheet stable, and the copper carries the signal. The exact qualified recipe—not one ingredient alone—determines who wins the board socket.
Woven fibers hold the laminate together and control expansion. Q-glass means quartz cloth: lower dielectric loss and expansion than ordinary electronic glass, but harder processing and qualification can raise cost.
Q-GLASS IS A TYPE OF ELECTRONIC CLOTHResin fills the cloth and electrically insulates copper layers. PTFE is a real ultra-low-loss option, but it can be harder to bond, drill and laminate than familiar thermoset systems.
PTFE IS CHEMISTRY, NOT A COMPANY OR BOARDCopper carries electrical signals. At very high speed, rough copper wastes more energy, so smoother HVLP-class foil and tighter process control matter.
LOSS COMES FROM BOTH DIELECTRIC + CONDUCTORThe CCL maker combines the ingredients. A PCB fabricator then patterns, drills, plates and stacks the laminate into the actual switch, midplane or accelerator board.
FORMULA + YIELD + CUSTOMER QUALIFICATION = SOCKETPrimary product sources show PTFE-based CCL used where extremely low transmission loss matters. It does not prove that one supplier has passed an AI-server qualification or reached material revenue.
The threat is losing a qualified formula or customer share to Shengyi, Nan Ya, Taiflex or another laminate vendor. If Elite Material qualifies its own PTFE or hybrid system, the same transition can be an opportunity.
M9 is used as market shorthand for a next low-loss board-material tier. M10 remains earlier channel terminology. Ask which board, customer specification, resin system and qualification stage the speaker means.
04 / Word decoder
Whenever you read “substrate shortage,” force the speaker to name the substrate. The investment chain changes completely depending on which one they mean.
The base material on which semiconductor devices are fabricated, usually a silicon wafer.
UPSTREAM: SUMCO, Shin-Etsu / USER: TSMC, Samsung, IntelA fine-pitch multilayer bridge between the die package and the much larger PCB. High-end versions often use ABF.
MATERIAL: Ajinomoto ABF / MAKERS: Ibiden, Shinko, Unimicron, Kinsus, AT&SA dense routing layer beside or under compute and HBM. It can use silicon, RDL, organic, or future glass approaches.
PLATFORMS: CoWoS, EMIB, Foveros / WATCH: glass core, TGVSometimes people loosely call the dielectric base of a PCB a substrate. The more precise terms are laminate, CCL, or PCB material.
CHAIN: glass cloth + resin + copper foil > CCL > PCB05 / Physical reality check
Use this when a headline jumps from chips to boards or from packaging to optics. It separates the compute package, the server board, and the network between servers.
CoWoS is a TSMC advanced-packaging family. It places compute dies and HBM stacks side by side on an interposer or dense redistribution wiring layer, then connects the module to a package substrate. It is package construction, not just a test step.
The IC substrate fans tiny die connections out to a larger solder-ball grid. The PCB is the much larger board that carries the packaged accelerator, CPU, NIC, VRMs, connectors, and MLCCs. Electronic glass cloth lives inside the CCL layers of that PCB, embedded in resin below the copper traces.
Optical links send data through fiber once bandwidth or distance makes copper inefficient. CPO puts optical engines close to a network-switch ASIC, shortening the electrical path. It is chiefly a networking architecture, not the GPU/HBM packaging method.
Read vertically for what sits on what inside a compute module. Read across at the bottom for how the server reaches a switch, CPO or a pluggable optical module, and then fiber.
1 / Compute and memory sit side by side
The physical stack does not change: DRAM dies still sit above a logic or base die and connect to the accelerator through advanced packaging. What can change is who specifies the interfaces, owns the custom logic and yield learning, controls qualification, and secures capacity. Those control points decide whether more value stays with the memory supplier, migrates to the accelerator buyer, or accrues to the integration and test layer.
SK hynix, Samsung and Micron can capture more than commodity bits when they own differentiated integration knowledge.
NVIDIA or a custom-ASIC buyer can pull value upstream if its scale and architecture make suppliers build to its system specification.
TSMC, memory packaging lines, OSATs and test vendors matter more as the cost of a late defect rises.
All five architectures send light through fiber, but they place conversion at different distances from the ASIC. LPO and XPO extend the replaceable pluggable boundary; Open CPX formalizes a socketed near-package engine; CPO integrates the engine most tightly beside the ASIC.
The switch sends a high-speed electrical signal along copper traces to a removable transceiver at the PCB edge. The transceiver makes light, then fiber carries it onward.
What is sold: a discrete optical module, plus the PCB electrical channel it must reach.
The ASIC package and optical engine sit close together on a common high-performance substrate or board. Separate test and possible socket-level rework can improve yield and serviceability, but the connector adds loss and standardization risk.
Trade-off: captures much of the power benefit while preserving supply-chain flexibility, testability and replacement boundaries.
The switch ASIC and optical engine sit in very close proximity, often within a common package assembly. The electrical route is shortest; the optical fiber leaves near the switch package.
What changes: fewer inches of very-high-speed copper, but tighter optical packaging, fiber attach, thermal design and serviceability.
Broadcom disclosed Bailly customer delivery in March 2024, and NVIDIA says Spectrum-X Ethernet Photonics is in production. That invalidates the blanket “zero shipments” framing. OCI standardization makes optical scale-up more credible, but broad accelerator-side volume, attach rate and bill of materials remain scenarios to prove.
“InP substrate” is a semiconductor wafer beneath an optical device—not the ABF package substrate below a GPU. Silicon photonics can modulate and route light efficiently, but an InP laser commonly supplies the photons.
These names sit at different product stages. A company can participate in all three, but capability, customer qualification, yield and volume revenue must be proved separately.
COSA is vendor shorthand for a chip-on-submount optical-assembly platform. It attaches, aligns, packages and tests EML or CW laser dies before they enter a finished module.
ELI5: package the tiny light bulb so another product can use it.
TRX means transceiver: it converts electrical bits to light and back. An active optical cable fixes optical engines to both cable ends. 400G and 800G name the link speed generation.
Yield: the share that passes. The cited 99% for redesigned 400G and 70% for ramping 800G are separate channel claims, not a contradiction or audited fact.
ELSFP is a hot-swappable external laser-source form factor. It keeps a high-power CW laser away from the hot switch ASIC, then sends steady light into the nearby CPO optical engine.
Pilot production: engineering or low volume. It is not the same as qualified high-volume shipments or material revenue.
An EML combines emission and modulation on one InP chip. A CPO silicon-photonics engine can share a higher-power external CW-DFB laser across lanes. The die count may fall while optical power, packaging, reliability requirements and value per die rise.
$8 → $30AUTHOR MODEL: CW-DFB LASER VALUE PER PORT, PLUGGABLE TO CPO; SCALE-UP CASE CAN REACH $60The falsifier is equally important: new high-power capacity, better yield or alternative VCSEL architectures could remove the laser premium before scale-up volume arrives.
Fine-pitch electrical fan-out below a chip or package. It remains necessary in CPO systems.
Server or switch board that carries chips, passives, copper routing and connectors. CPO reduces only part of its fastest electrical reach.
The interface that modulates and receives light near the switch ASIC. This is the architecture-specific piece.
The physical optical medium carrying photons to another switch, rack or cluster. This is the transmission path.
Sell the tools used to make semiconductors.
ASML · Applied Materials · Lam · KLABuy and run SPE to fabricate customer chip designs.
TSMC · SMIC · Hua HongOwn architecture and software, but usually outsource wafer production.
NVIDIA · Cambricon · HygonTurn dies into modules, then modules into servers and networks.
TSMC / ASE / Amkor · substrate · PCB · optics06 / Advanced testing overlay
As GPU chiplets, HBM and hybrid bonds accumulate inside a system, discovering a defect late destroys more embedded value. The response is multiple test insertions before, during and after advanced packaging, plus product-specific branches such as optical-engine testing.
Find bad wafer sites, logic dies and memory stacks before they enter a high-value multi-die package.
Check microbumps, TSVs, hybrid bonds, interposer links and power delivery as components are combined.
Final test, burn-in and workload- or rack-level validation catch failures that only appear under speed, heat or interaction.
Probe cards touch die pads while chips are still on the wafer. Electrical tests build the wafer map used for downstream selection.
Only dies judged functional should consume scarce HBM, interposer area, substrate and package capacity.
Validate DRAM stacks, base dies, TSV paths and chiplets before or during heterogeneous integration.
Check hybrid bonds, microbumps and die-to-die links whose defects may not be visible in a single-die test.
Automated test equipment exercises the assembled accelerator package through sockets, contactors and load boards.
Temperature and voltage stress screen early-life failures. Longer stress time consumes sockets, handlers and thermal capacity.
Board-like conditions and realistic workloads expose high-speed, memory, power and thermal interactions that structural tests can miss.
Exercise accelerators, switches, memory, power and cooling together to expose cluster-level interactions, marginal links and thermal or firmware instability.
For optical engines and network packages—not every accelerator—validate electrical-to-optical conversion, laser coupling, modulators, detectors, fiber attach, alignment and performance across temperature. Known-good-die screening matters before expensive CPO assembly. Primary product evidence now supports Teradyne Photon 100, Advantest/OpenLight, FormFactor Pharos and Keysight integrated-photonics tools as named public-equity exposures; CPO-specific revenue materiality remains unproven.
OSATs and foundry/package integrators operate wafer sort, package test, burn-in and system-level capacity.
Automated testers generate and measure high-speed electrical and optical patterns. Advantest and Teradyne are representative vendors.
FormFactor and peers supply probe cards and photonics interfaces; sockets, contactors and load boards connect the device to the tester.
Handlers, temperature control, vision, alignment and Keysight-class photonic instrumentation make demanding tests repeatable.
07 / Demand to capacity
This is the missing economic bridge in the linked article. Model usage creates supply-chain demand only when it produces enough useful, billable work to support leased or owned compute, financed construction, and energized capacity.
Consumer reach is one S-curve. Tokens, tool calls and validation work per user are a second. Agentic workloads can keep the second curve rising after user growth slows, but raw token volume is not the same as economic value.
USEFUL AI DEMAND ≈ ACTIVE USERS × TASKS PER USER × TOKENS PER TASK × EXECUTION / VALIDATION WORK
OWNER COVERAGE = (COMPUTE RENT + SERVICES) ÷ (DEPRECIATION + POWER + FINANCING + OPERATIONS)
Use build cost, depreciation, development yield, power, occupancy, contract term and residual value. This is the data-center, neocloud, REIT or infrastructure-fund view.
RENTER COVERAGE = TOKEN / APPLICATION REVENUE ÷ (COMPUTE LEASE + INFERENCE OPERATIONS)
Use the annual rent or cloud bill, not the owner's build-cost depreciation. Training and inference must also be separated because only inference ties directly to current token revenue.
The article compares roughly $30B of revenue per GW with about $8–10B of annualized owner build cost to argue for about 3× coverage. It later cites roughly $20B per GW per year of compute rent. If the model lab rents the capacity, $20B is the relevant renter denominator, so coverage is closer to 1.5× before other operating costs. Never mix the owner's return with the tenant's gross margin.
ALSO SEPARATE: TRAINING VS INFERENCE · CONTRACTED VS ENERGIZED GW · RESERVED VS USED CAPACITY · ARR VS CASH · AUTHOR ESTIMATE VS COMPANY DISCLOSUREFinancing and take-or-pay demand pull GPUs, HBM, CoWoS, substrates, boards, racks, optics, grid equipment and cooling. Power and package capacity can remain binding.
Watch energization, customer concentration, lease spreads, GPU utilization and project phasing. CPU, DRAM, SSD and network demand can broaden as agents perform more execution work.
Excess capacity can hurt leveraged owners, neoclouds and late equipment orders through price compression or cancellations. Model labs and applications may benefit from cheaper compute.
08 / Bottleneck lab
Pick a scenario. The panel separates the first-order bottleneck, second-order read-through, and the evidence that would falsify the thesis.
09 / PM checklist
A bottleneck is investable when the constraint is qualified, durable, economically captured, material to earnings, and underappreciated. A shortage headline alone only clears the first gate.
Does the new rack or package use more area, layers, watts, ports, fibers, capacitors, or test seconds?
Count qualified vendors, customer redesign time, reliability testing, and yield learning.
Track tool lead time, permits, cleanrooms, specialized labor, utilization, and ramp yield.
Prefer the firm with IP, process control, allocation rights, or irreplaceable qualified capacity.
Map revenue exposure, incremental margins, customer concentration, and required capex.
Separate sampling, qualification, equipment orders, capacity readiness, shipments, and revenue.
10 / Source anchors
The page is an educational framework, not a live supply forecast. Representative company names show where firms sit, not a recommendation or a claim of direct customer relationships. Broker and social-media exhibits are labeled as secondary sources.